1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a semiconductor device, e.g., a positive-channel metal oxide semiconductor (pMOS) transistor device having improved leakage current (Ioff) and junction capacitance characteristics.
2. Discussion of the Related Art
In fabricating a semiconductor device, for example, a pMOS device for use in portable electronics devices, there is a trade-off between high-performance and low off-state leakage current characteristics of the pMOS device. To achieve high-performance (e.g., high-speed) characteristics, the leakage current may be decreased by suppressing a gate-induced drain leakage current to achieve a balanced interrelationship (i.e., a “tuning”) of a gate poly oxide layer, a spacer, etc. Leakage current may also be controlled through the process of forming a lightly doped drain and the wafer cleaning conditions. Such methods are disclosed, for example, in “Ultra-low Leakage 0.16 μm CMOS for Low Standby Power Applications” (IEEE International Electron Devices Meeting (IEDM) Technical Digest, 1999 , pp. 671-674) by C. C. Wu et al. and in “A Novel Double Offset-implanted Source/Drain Technology for Reduction of Gate-induced Drain Leakage with 0.12 μm Single-gate Low-power SRAM Device” (IEEE Letters, 2002 , Vol. 23 , pp. 719-721) by Sang-hun Seo et al. Another method for decreasing leakage current is disclosed in “Junction Capacitance Reduction Due to Self-aligned Pocket Implantation in Elevated Source/Drain NMOSFETs” (IEEE Transactions, 2001, Vol. 48, pp. 1969-1974) by Naruhisa Miura et al. Such methods, however, are costly and involve processes requiring time-consuming set-ups.